Oscilloscope Setup for SPI - Quick Guide
These instructions provide a quick setup for your oscilloscope for SPI monitoring. They will help you get a usable transaction on screen. From that starting point, you can explore clock polarity and phase, chip select timing, inter-byte gaps, signal integrity, and bus contention.
When setting up your oscilloscope, you need to know two parameters about your bus:
bus speed
operating voltage
You will need four channels to see the SPI bus:
SCK — serial clock
PICO — Peripheral In, Controller Out
POCI — Peripheral Out, Controller In
CS# — Chip Select, active low
Other signals may be useful, but without CS# you cannot reliably see transaction boundaries.
You will need the scope to be free-running to find your signals on the screen. Adjust the voltage to bring the waveforms on-screen. Once you have the signals visible, you can refine capture and timing.
Naming note: This guide uses PICO/POCI as these terms are widely adopted in datasheets (ST, Microchip, Raspberry Pi). Some vendors use COTI/CITO (NXP), and older documents may use MOSI/MISO. Arduino uses COPI/CIPO, but those terms are avoided here.
Channels
The essential SPI signals:
SCK
Idle high or low
Depends on CPOL.
PICO
Driven by controller
Data from controller to peripheral.
POCI
Driven by peripheral
Data from peripheral to controller.
CS#
Active low
Marks start and end of a transaction.
Optional signals for debugging: RESET#, INT, PWR. Always connect ground as well as the signals. Turn on each channel individually with the channel enable.
Start the scope running
Trigger – auto/continuous
RUN – enable
Voltage
Use the voltage scale and position controls to bring signals on-screen.
Voltage Scale
Initially 2 V/div.
SPI buses normally run at 3.3 V or 1.8 V logic levels.
Optional signals may differ in voltage. Refer to the schematic or datasheets.
A starting scale of 2 V/div will fit 4 channels comfortably on screen. After offsets are adjusted, you may reduce the scale for individual signals.
Voltage Offset
Initially 0 V. Use vertical position to spread signals evenly across the screen.
Zero all offsets, then separate traces so they don’t overlap. Typical layout: CS# top, SCK below, PICO/POCI at bottom.
Set Trigger
Source = CS#
Type = Falling Edge
Level = 0.5 V (or ~30% of bus voltage)
Offset = 0.0 s
Source and edge
Triggering on CS# ensures capture starts at the beginning of a transaction. If your device use CS, not CS# you will be looking for a rising edge, not falling.
If no CS# is available, use SCK and select an edge consistent with CPOL/CPHA.
Trigger level
Set trigger level to ~30% of bus voltage (falling) or 70% (rising).
5.0 V
2.5 V
1.5 V
3.5 V
3.3 V
1.65 V
1.0 V
2.0 V
1.8 V
900 mV
600 mV
1.2 V
1.0 V
500 mV
300 mV
700 mV
Remember, just because your oscilloscope recognizes a state change, your hardware may not.
Timing scale
Start with one or two bytes visible on screen.
SPI has one clock leading edge per bit. With 8 bits per byte, the byte time is:
100 kHz
10 µs
80 µs
10 µs/div
20 µs/div
1 MHz
1 µs
8 µs
1 µs/div
2 µs/div
10 MHz
100 ns
800 ns
100 ns/div
200 ns/div
25 MHz
40 ns
320 ns
50 ns/div
100 ns/div
50 MHz
20 ns
160 ns
20 ns/div
50 ns/div
Adjust timebase until you have clean edges visible and at least one full byte.
Sample rate
Your scope must sample at least twice the maximum clock frequency, but in practice 5–10× is recommended.
100 kHz
200 kSa/s
1 MSa/s
1 MHz
2 MSa/s
10 MSa/s
10 MHz
20 MSa/s
100 MSa/s
25 MHz
50 MSa/s
250 MSa/s
50 MHz
100 MSa/s
500 MSa/s
Checklist
Power on scope.
Connect probe ground.
Connect probes (SCK, PICO, POCI, CS#).
Enable channels.
Set voltage scale and offset.
Trigger on CS# (falling edge).
Adjust timebase for one byte or transaction.
Verify sample rate ≥ 5× SCK frequency.
This gives you a solid starting point for SPI capture. From here you can refine based on CPOL/CPHA mode, inter-byte gaps, and peripheral timing.
From here you can also start to explore:
Dual SPI.
Quad SPI.
Double Data Rate.
None SPI devices that are based on serial shift register transactions.
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